Freelance Analog IC Layout Engineer

--fabrice siracusa--

Postuler

Freelance Opportunity

We are building our freelancer bench for upcoming advanced full-custom analog layout projects. Location: Grenoble, France. Remote is possible with occasional on-site presence when needed.

Apply as a Freelancer View Technical Scope

Start window

4 to 6 months

Work mode

On-site / Remote

Focus

Analog full-custom layout

What we value

Silicon-ready mindset and clean verification closure
Strong methodology for matching and parasitic awareness
Ability to handle complex hierarchical TOP integration
Clear communication and milestone-driven delivery

Quick note

Please avoid sharing confidential design details in the form. High-level project examples are enough for screening.

Technical Requirements

We are looking for strong hands-on expertise in the full-custom layout flow and physical sign-off.

Cadence Virtuoso Layout XL
Physical verification: DRC, LVS
Parasitic extraction (PEX), sign-off oriented
Advanced CMOS nodes (typically below 28nm)
Analog layout best practices: matching, symmetry, shielding, guard rings
Awareness of variations, coupling effects, and IR-drop considerations
Full-custom physical verification and closure methodology
TOP-level integration and complex hierarchical interconnect management

Typical Deliverables

The scope depends on the project phase. Common deliverables include:

Block layout execution

Hierarchical assembly

DRC closure support

LVS closure support

PEX extraction and review

Coupling and noise mitigation

Power routing and IR-drop awareness

Final physical sign-off readiness

Nice to have

Experience across multiple advanced nodes
Mixed-signal blocks (ADC, PLL, LDO, sensor front-ends)
Comfortable in reviews and cross-team coordination

Interested in collaborating with us?

Submit your profile and we will reach out for a short technical discussion to share the project scope and expected contract duration.

Apply Now

Postuler