Mission context

 As part of its development and strong growth, Xdigit is strengthening its technical team.

As a digital design engineer, you will study, specify, model, simulate and verify digital blocks and subsystems.

Working closely with other digital designers and physical implementation engineers, you will manage the various phases of specification, digital block architecture definition, design, simulation and testing.

You report directly to the CTO.

Join the Xdigit adventure and contribute your talent to the company's growth. The position will be based at our Grenoble site (38) or at our Meyreuil site (13) in the Bouches-du-Rhône region.

Main tasks

• Write low-level specifications for blocks to be developed.
  
• Participate in cost estimates and development schedules for digital blocks.
  
• Perform system modeling
  
• Perform RTL coding (VHDL/Verilog).
  
• Participate in the drafting of validation plan specifications for the blocks designed.
  
• Co-develop testbenchs (systemVerilog/SystemC/VHDL/Verilog ...)
  
• Perform validation by simulation and code coverage.
  
• Define timing and consumption constraints, in interaction with routing placement.
  
• Perform block performance verification tasks: coverage rate, frequency, maximum power consumption, area.
  
• Carry out digital synthesis using associated techniques (DfT, scan compression, built-in self-test (BIST), JTAG, etc.).
  
• Write design reports (specification review).
  
• Participate in characterization and testing.
  
• Participate in improving the verification flow of digital design, functional modes and test modes.
  
• Participate in internal design reviews and external technical discussions with customers, acting as technical guarantor of circuit performance in accordance with specifications.
  

Skills

• Cursus ingénieur, Master ou Doctorat dans la conception et l’évaluation de circuits numériques avec 5 ans d’expérience minimum.
• Maitrise du systemC.
• Connaissance des interfaces MIPI DSI, USB, Série, …
• Maitrise des outils de simulation numériques et de synthèse.
• Connaissance des outils de preuve formelle et génération de pattern ATPG.
• Maitrise des langages VHDL, Verilog, SystemVerilog et C/C++.
• Bon niveau d’Anglais nécessaire à la communication avec les fournisseurs et les clients.

How to be

• Curious, autonomous and organized.
  
• Results and customer satisfaction oriented.
  
• Ability to adapt.
  
• Ability to share and transfer information and knowledge.
  
• Proactive and proactive in solving problems and improving existing processes.

Salary and package

• Fixed salary according to profile (Syntec agreement)
  
• 10 days annual RTT
  
• Health insurance
  
• Luncheon vouchers
  
• 1 to 2 teleworking days per week.